Sumitra
Singar

Sumitra Singar, a faculty member with the Faculty of Computing Skills Education, is a doctorate in Low Power VLSI Design from Mody University of Science and Technology, Lakshmangrah, Rajasthan. She holds a Masters and a Bachelors in Electronics and Communication Engineering from Rajasthan Technical University, Kota. She holds a polytechnic diploma in Electronics from the Government Women’s Polytechnic College, Ajmer. Prior to joining BSDU, she worked as an assistant professor in the Poornima group of colleges in their Poornima Institute of Engineering and Technology, Jaipur. She has almost 9 years of experience in teaching, research and administration in engineering and skill education domain. She has published her research work in different reputed SCI/SCOPUS Indexed Journals, International/National conferences, SCOPUS Indexed book chapters and one national patent. She also reviewed some reputed journal papers.

She has interest in the field of Internet of Things, Wireless Sensor Networks, Computer Networking, Python Programming, Machine Learning and Artificial Intelligence and 5G with IoT. Her specialization includes circuit design and the simulation of digital circuits and image processing.

1. “Near Threshold Operation Based a Bug Immune DET-FF for IoT Applications”, Lecture Notes in Networks and Systems (Proceedings of International Conference on Recent Trends in Computing), ISBN 978-981-19-8824-0, ISSN 2367-3370, Springer (SCOPUS), March 2023.

2. Patent- “IoT based book integrated device for learning, memorization and monitoring: alternate of mobile, laptop and tab”, pp-67362, Patent Office Journal No. 42/2022 Dated 21/10/2022.

3. “Literature Survey: Single Image Dehazing using Deep Learning Techniques”, International Journal of Food and Nutritional Sciences (UGC), e-ISSN 2320-7876, Volume 11, S Issue 3, Dec 2022.

4. “A Comparative Analysis of Dark Channel Prior Techniques Using Single Image Dehazing”, Neuroquantology (SCOPUS), ISSN: 1303-5150, Vol. 20, Nov 2022.

5. “Classification of homogenous and non-homogenous single image dehazing techniques”, Communications in Computer and Information Science, ISSN 1865-0929, pp. 479–493, vol. 1591, Springer (SCOPUS), May 2022.

6. “Single Image Dehazing techniques for different types of Hazy Images”, Applied Computational Technologies, ICCET-2022, ISBN: 978-981-19-2719-5, Vol. 303, pp. 383-394, Springer (SCOPUS), May 2022.

7. Book- “Low Power Fault Tolerant Latches and Flip-Flops-Design and performance Analysis”, in LAMBERT Academic Publishing, ISBN: 978-613-9-45302-3, Pages 152, Feb 2019.

8. “Low Glitch DET-FF for Low Power Integrated Applications”, in International Conference on Signal Processing and Integrated Networks(SPIN), DOI: 10.1109/SPIN.2019.8711740, SCOPUS index, March 2019.

9. “Power Analysis of Novel Glitch Resistant DET-FF”, in IJEDR, ISSN: 2321-9939, Vol. 7, Issue no. 1, pp. 96-100, Jan 2019.

10. “Fault-Free D-Latch Configurations for Low Power Applications”, Journal of Nanoelectronics and Optoelectronics (SCI, SCOPUS), ISSN/ISBN: 1555-1318, vol. 13, no. 5, pp. 701-707, May 2018.

11. “A Glitch Free Novel DET-FF in 22nm CMOS for Low Power Application”, Journal of Nanotechnology (SCOPUS), Hindawi, ISSN/ISBN: 1687-9503, vol. 2018, Article ID 2934268, 10.1155/2018/2934268, pp. 1-6, March 2018.

12. “Design and Performance Analysis of Advanced Glitch Free DET-FF in 45nm CMOS Technology”, International Journal of Electronics, Electrical and Computational System, Volume 7, Issue 2, February 2018.

13. “Unique Robust Fault Resistant D-Latch for Low Power Applications” in International Conference on Computer, Communications and Electronics (Comptelix), pp. 16-20, 978-1-5090-4708-6/17/$31.00 ©2017 IEEE, July 01-02, SCOPUS index, 2017.

14. “Near threshold impact on delay in a low power D-latch with technology variations”, Book chapter: Renewable Energy and Smart Grid Technology-1st Edition-Bloomsbury, pp. 265-271, Feb. 2017.

15. “Novel Fault Resistant D-Latch for Low Power VLSI Design”, in International Journal of Engineering and Manufacturing Science (RIP), Volume 7, Number 2 (2017), pp. 383-391, Dec, 2017.

16. “A Survey on Runtime-Leakage Reduction Techniques in VLSI Design”, in International Journal of Engineering Science and Computing, Vol. 6 Issue No. 7, pp. 1986-1988, July 2016.